Moore's Law
IBM and Samsung have developed a first-of-a-kind process to build silicon nanosheet transistors that will enable 5 nanometer chips. The resulting increase in performance will help accelerate artificial intelligence, the Internet of Things (IoT) and other data-intensive applications delivered in the cloud. The power savings alone might mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.
"The economic value that Moore’s Law generates is unquestionable. That’s where innovations such as this one come into play, to extend scaling not by traditional ways but coming up with innovative structures."
IBM and Samsung, have announced the development of an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips.The breakthrough means that silicon technology has yet again extended the potential of Moore's Law.
Less than two years after developing a 7nm test node chip with 20 billion transistors, the researchers involved have paved the way for 30 billion switches on a fingernail-sized chip.
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The resulting increase in performance will help accelerate artificial intelligence, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices, before needing to be charged.“The economic value that Moore’s Law generates is unquestionable. That’s where innovations such as this one come into play, to extend scaling not by traditional ways but coming up with innovative structures,” says Mukesh Khare, vice president of semiconductor research for IBM Research.
Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which is the blueprint for the semiconductor industry up through 7nm node technology.
IBM scientists at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY prepare test wafers with 5nm silicon nanosheet transistors, loaded into the front opening unified pod, or FOUPs, to test the process of building 5nm transistors using silicon nanosheets. Image Source - Connie Zhou / IBM
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| Pictured: a scan of IBM Research Alliance’s 5nm transistor, built using an industry-first process to stack silicon nanosheets as the device structure – achieving a scale of 30 billion switches on a fingernail-sized chip that will deliver significant power and performance enhancements over today’s state-of-the-art 10nm chips. Image Source - IBM |
Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES stated. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”
IBM Research has explored nanosheet semiconductor technology for more than 10 years. This work is the first in the industry to demonstrate the feasibility to design and fabricate stacked nanosheet devices with electrical properties better than FinFET architecture.
The scientists used the same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node and its 20 billion transistors to the nanosheet in the new transistor architecture. Using EUV lithography, the width of the nanosheets could be adjusted continuously, all within a single manufacturing process or chip design.
This adjustability allowed for the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production.
Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute said that, “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities.”
Full implementation of this technology will still require 10 to 15 years of further development according to some reports.
The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan.
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