Extending and Expanding Moore's Law with 3D Chips

Almost 50 years after Gordon Moore forecast the path toward faster, cheaper chips, we've miniaturized electronic components so much that we're increasingly colliding with fundamental physical limitations. Wires only four atoms long by one atom tall have been created.  The days of simple transistor scaling are long behind us with the latest, greatest chips being more of a hodgepodge of materials and design tweaks. These chips also leak a lot of power, and contain transistors that are so variable in quality they're difficult to run as intended.

Fortunately, chipmakers are pursuing a pair of innovations that will give dramatic boosts in the two categories that really count: performance and power consumption. In both cases, the idea is to build up and into the third dimension. And manufacturers will do it at the level of both the individual transistor and the full microchip. In 2012, the chip will start to become the cube.

Until recently, microprocessor transistors have been flat, built into the plane of the silicon. Each field-effect transistor on a chip contains four parts: a source, a drain, a channel that connects them, and a gate on top that controls the current flow through the channel. Only the gate and a thin layer of insulator beneath it rest above the silicon.

However, this past May, Intel unveiled its plans for the first big move away from the flat transistor. After months of gearing up production, the new transistors, which are built into a processor code-named Ivy Bridge, will make their way onto the market during the first half of 2012.  This will replace the Sandy Bridge format, and is already on the specification sheets of many manufacturers.

In many ways, 3D is nothing new to chipmakers. Flash memory, for example, is stacked to cut down on volume and boost speed. But chip stacking has been limited by wiring problems. Today's interconnects don't run through the silicon itself but instead go millimeters around it, impeding speedy signaling and sapping power along the way. Horizontal real estate is also precious. The thinnest interconnects are still 25 micrometers wide, and they must be packed along the edges of a chip, putting strict limits on how many input/­output connections any one chip can handle.

Thus the attractiveness of going vertical, connecting one chip to another with copper lines that go straight through the silicon. If chipmakers can cheaply manufacture these through-­silicon vias (TSVs), they can pack many more connections side by side using much slimmer wires. Going through chips instead of around the side will also reduce the length of interconnects from milli­meters to 50 μm or even less—as thin as individual wafers can be made. The potential advantages are huge. Samsung, one of several companies working on making dynamic RAM memory stacks connected by TSVs, has estimated that the switch to vertical interconnects will cut power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent.

In fact, the most dramatic achievement in the coming year might be a simple stacking configuration that's often called 2.5D. This approach takes advantage of TSVs by running them through an ­intermediate layer of silicon called an interposer, which sits between an IC and a PC board. By one measure, the technology is more or less two-dimensional. All the packages you choose to put in a device—RF receivers, graphics units, memory, logic—still sit on the plane of the mother­board. But instead of copper traces running across the motherboard from package to package, in this configuration copper connections run through TSVs and past the interposer layer, where the vertical wiring is connected in a series of horizontal patterned layers. By moving all the connections outside the plane, device makers can place chips right next to one another, saving space and power.

There are other big questions that will need to be addressed as manufacturers contemplate making more complicated chip stacks. How do you make sure that two chips made by different companies can be connected? Is there an inexpensive way to verify that each layer in a package works? And if the finished IC doesn't work, how do you determine who is responsible for the failure?

Foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) has been struggling with this last question as the company tries to ramp up interposer production by its target date in the second half of 2012. "When we started TSV development, we did it the conventional way," says Doug Chen-Hua Yu, who heads up interconnect and packaging R&D at the company.

Yu says TSMC typically sends completed wafers to be packaged by assembly companies known as OSATs (outsourced subassembly and test providers). But the thinned wafers are too easily damaged. When that happens, "it's very hard to go back and decide who did what wrong," Yu says. "It [could be] the wafer fab or the OSAT or FedEx. We don't know."

Even if wafers are inspected carefully before and after shipping, there could be latent damage that emerges only after processing. As a result, Yu says, TSMC is now hoping to do most of its TSV wafer manufacturing and packaging in-house.

Liability issues, industry standards, and a host of other manufacturing matters still need to be sorted out. But no one seems to foresee any insurmountable hurdles to 3D TSV technology. "It's changing how we do the whole supply chain. That's why it's taking such a long time to get this on the ground and running," says Sematech's Arkalgud. "But once it happens, it will be going for quite some time."

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