Computers  

Researchers have build 3D “high-rise” chips that could leapfrog the performance of the single-story logic and memory chips on today’s circuit cards, which are subject to frequent traffic jams between logic and memory.

Researchers at Stanford University have built a new multi-layered "high-rise" chip that could significantly outperform traditional computer chips, taking on the hefty workloads that will be needed for the Internet of Things, Big Data and to continue the exponential trends in computation after Moore's Law.

By using nanotechnology, the new chips are built with layers of processing on top of layers of memory, greatly cutting down on the time and energy typically needed to move information from memory to processing and back.

Max Shulaker, a researcher on the project and a Ph.D candidate in Stanford's Department of Electrical Engineering, said they have built a four-layer chip but he could easily see them building a 100-layer chip if that was needed.

"The slowest part of any computer is sending information back and forth from the memory to the processor and back to the memory. That takes a lot of time and lot of energy," Shulaker told Computerworld. "If you look at where the new exciting apps are, it's with big data… For these sorts of new applications, we need to find a way to handle this big data."

The conventional separation of memory and logic is not well-suited for these types of heavy workloads. With traditional chip design, information is passed from the memory to the processor for computing, and then it goes back to the memory to be saved again.

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In relative terms, that takes a lot of energy and time – way more than the computation itself.

"People talk about the Internet of Things, where we're going to have millions and trillions of sensors beaming information all around," said Shulaker. "You can beam all the data to the cloud to organize all the data there, but that's a huge data deluge. You need [a chip] that can process on all this data… You want to make sense of this data before you send it off to the cloud."

That, he noted, would make working with the cloud, as well as with the Internet of Things, more efficient.

The new high-rise chip is based on three emerging technologies, according to Stanford.

The researchers, led by Subhasish Mitra, a Stanford associate professor of electrical engineering and computer science, and H.S. Philip Wong, a professor in Stanford's school of engineering, used carbon nanotube transistors instead of silicon and replaced typical memory with resistive random-access memory (RRAM) or spin-transfer torque magnetic random-access memory (STT-RAM). Both use less power and are more efficient than traditional memory systems.

"For all of these Internet of Things applications, all of them would run much, much more efficiently and much, much faster. For way less energy, you'd be able to do way more work."

The third new technique is to build the logic and memory technologies in layers that sit on top of each other in what scientists describe as "high-rise" structures.

"The connectivity between the layers increases by three orders of magnitude or a thousand times the benefit in bandwidth of how much data you can move back and forth," Shulaker said. "For all of these Internet of Things applications, all of them would run much, much more efficiently and much, much faster. For way less energy, you'd be able to do way more work."

Shulaker said they've built four-layer chips but could build many more layers. Now they're trying to figure out what size structure gives the most benefit for the cost of the build.

“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.” Wong said the prototype chip unveiled at the IEEE International Electron Devices Meeting shows how to put logic and memory together into three-dimensional structures that can be mass-produced.

The researchers also said the chips could be built in a traditional chip fabrication plant without much retooling. Shulaker declined to say what kind of interest the researchers are receiving from commercial computer chip manufacturers but did say they are collaborating with industry.


SOURCE  Computer World

By 33rd Square

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 Memory  

The next-generation computer memory that can store about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology — is now a step closer to to mass production.

Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

First discovered five years ago, Rice’s silicon oxide memories are a type of two-terminal, “resistive random-access memory” (RRAM) technology. In a new paper available online in the American Chemical Society journal Nano Letters, a Rice team led by chemist James Tour compared its RRAM technology to more than a dozen competing versions.

“This memory is superior to all other two-terminal unipolar resistive memories by almost every metric,” Tour said. “And because our devices use silicon oxide — the most studied material on Earth — the underlying physics are both well-understood and easy to implement in existing fabrication facilities.” Tour is Rice’s T.T. and W.F. Chao Chair in Chemistry and professor of mechanical engineering and nanoengineering and of computer science.

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

"Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory."

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

The rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices.
Image Source - Tour Group/Rice University 

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

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“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.


SOURCE  Rice University

By 33rd Square

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