Carbon Nanotubes  

Researchers are developing a new generation of computers with processors based on carbon nanotubes or CNTs. CNT processors and memory stacked in layers on chips might put supercomputer power into a smartphone in the future.

With support from the National Science Foundation electrical engineer H.S. Philip Wong, and computer scientist, Subhasish Mitra, at Stanford University are working with IBM to develop a new generation of computers with processors made from tiny carbon nanotubes 50,000 times thinner than a human hair.

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In a few years carbon nanotube-based processors could begin to replace bulky silicon chips and bring Moore's Law into a new paradigm.

"Today we have incredible computing that has changed our lives," states Mitra, "But to be able to do more so we need massive amount of performance. For example what today runs on a supercomputer, we should be able to run on a cell phone."

So far the researchers carbon nanotube chip has rather modest functionality. It runs a robotic arm that shakes hands. But this was a big advance, years in the making. The Stanford team had to overcome some big design and device fabrication hurdles to get this far.

Even though it may be the perfect material to make the perfect transistor, the engineering challenge of producing carbon nanotubes on a large scale with billions and billions of transistors on the same chip or even in multiple layers of the chip is a great challenge.

Developing a multi-layered chip carbon nanotube transistors and memory devices stacked one on top of the other is the ultimate aim for the researchers.

According to Wong, "Today silicon chips are two-dimensional, just like in a landscape you have
houses and then your street and so on, what do people in big cities do? They build high-rises."

"The fact of the matter is, if you don't work on it, if you don't put effort into it, this is not going to happen."

Today, much of our global economy runs on the expectation that computers will continue to get faster
devices smaller and costs will keep going down. "The fact of the matter is, if you don't work on it, if you don't put effort into it, this is not going to happen," states Wong.

Wong sees this high-rise architecture as a gateway to vast improvements in computing speed and performance. "You can look forward into the future I would say you ain't seen nothing yet!"

SOURCE  Stanford University

By  33rd Square

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 Computers  

Researchers have build 3D “high-rise” chips that could leapfrog the performance of the single-story logic and memory chips on today’s circuit cards, which are subject to frequent traffic jams between logic and memory.

Researchers at Stanford University have built a new multi-layered "high-rise" chip that could significantly outperform traditional computer chips, taking on the hefty workloads that will be needed for the Internet of Things, Big Data and to continue the exponential trends in computation after Moore's Law.

By using nanotechnology, the new chips are built with layers of processing on top of layers of memory, greatly cutting down on the time and energy typically needed to move information from memory to processing and back.

Max Shulaker, a researcher on the project and a Ph.D candidate in Stanford's Department of Electrical Engineering, said they have built a four-layer chip but he could easily see them building a 100-layer chip if that was needed.

"The slowest part of any computer is sending information back and forth from the memory to the processor and back to the memory. That takes a lot of time and lot of energy," Shulaker told Computerworld. "If you look at where the new exciting apps are, it's with big data… For these sorts of new applications, we need to find a way to handle this big data."

The conventional separation of memory and logic is not well-suited for these types of heavy workloads. With traditional chip design, information is passed from the memory to the processor for computing, and then it goes back to the memory to be saved again.

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In relative terms, that takes a lot of energy and time – way more than the computation itself.

"People talk about the Internet of Things, where we're going to have millions and trillions of sensors beaming information all around," said Shulaker. "You can beam all the data to the cloud to organize all the data there, but that's a huge data deluge. You need [a chip] that can process on all this data… You want to make sense of this data before you send it off to the cloud."

That, he noted, would make working with the cloud, as well as with the Internet of Things, more efficient.

The new high-rise chip is based on three emerging technologies, according to Stanford.

The researchers, led by Subhasish Mitra, a Stanford associate professor of electrical engineering and computer science, and H.S. Philip Wong, a professor in Stanford's school of engineering, used carbon nanotube transistors instead of silicon and replaced typical memory with resistive random-access memory (RRAM) or spin-transfer torque magnetic random-access memory (STT-RAM). Both use less power and are more efficient than traditional memory systems.

"For all of these Internet of Things applications, all of them would run much, much more efficiently and much, much faster. For way less energy, you'd be able to do way more work."

The third new technique is to build the logic and memory technologies in layers that sit on top of each other in what scientists describe as "high-rise" structures.

"The connectivity between the layers increases by three orders of magnitude or a thousand times the benefit in bandwidth of how much data you can move back and forth," Shulaker said. "For all of these Internet of Things applications, all of them would run much, much more efficiently and much, much faster. For way less energy, you'd be able to do way more work."

Shulaker said they've built four-layer chips but could build many more layers. Now they're trying to figure out what size structure gives the most benefit for the cost of the build.

“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.” Wong said the prototype chip unveiled at the IEEE International Electron Devices Meeting shows how to put logic and memory together into three-dimensional structures that can be mass-produced.

The researchers also said the chips could be built in a traditional chip fabrication plant without much retooling. Shulaker declined to say what kind of interest the researchers are receiving from commercial computer chip manufacturers but did say they are collaborating with industry.


SOURCE  Computer World

By 33rd Square

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