Moore's Law  

IBM has announced it is investing $3 billion for R&D in two research programs to push the limits of chip technology and extend Moore’s law. The research programs are aimed at “7 nanometer and beyond” silicon technology and developing alternative technologies for post-silicon-era chips using entirely different approaches.

IBM has announced it is investing $3 billion over the next 5 years in two broad research and early stage development programs to push the limits of chip technology needed to meet the emerging demands of cloud computing and Big Data systems. These investments will push IBM's semiconductor innovations from today’s breakthroughs into the advanced technology leadership required for the future.

The first research program is aimed at so-called “7 nanometer and beyond” silicon technology that will address serious physical challenges that are threatening current semiconductor scaling techniques and will impede the ability to manufacture such chips.

The second is focused on developing alternative technologies for post-silicon era chips using entirely different approaches, which IBM scientists and other experts say are required because of the physical limitations of silicon based semiconductors.

IBM will be investing significantly in emerging areas of research including carbon nanoelectronics, silicon photonics, new memory technologies, and architectures that support quantum and cognitive computing.

"The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?"

These teams will focus on providing orders of magnitude improvement in system level performance and energy efficient computing. In addition, the company will continue to invest in the nanosciences and quantum computing--two areas of fundamental science where IBM has remained a pioneer for over three decades.

IBM Researchers and other semiconductor experts predict that while challenging, semiconductors show promise to scale from today's 22 nanometers down to 14 and then 10 nanometers in the next several years.  However, scaling to 7 nanometers and perhaps below, by the end of the decade will require significant investment and innovation in semiconductor architectures as well as invention of new tools and techniques for manufacturing.

"The question is not if we will introduce 7 nanometer technology into manufacturing, but rather how, when, and at what cost?" said John Kelly, senior vice president, IBM Research. "IBM engineers and scientists, along with our partners, are well suited for this challenge and are already working on the materials science and device engineering required to meet the demands of the emerging system requirements for cloud, big data, and cognitive systems. This new investment will ensure that we produce the necessary innovations to meet these challenges."

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Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. Their increasingly small dimensions, now reaching the nanoscale, will prohibit any gains in performance due to the nature of silicon and the laws of physics. Within a few more generations, classical scaling and shrinkage will no longer yield the sizable benefits of lower power, lower cost and higher speed processors that the industry has become accustomed to.

With virtually all electronic equipment today built on complementary metal–oxide–semiconductor (CMOS) technology, there is an urgent need for new materials and circuit architecture designs compatible with this engineering process as the technology industry nears physical scaling limits of the silicon transistor.

Beyond 7 nanometers, the challenges dramatically increase, requiring a new kind of material to power systems of the future, and new computing platforms to solve problems that are unsolvable or difficult to solve today. Potential alternatives include new materials such as carbon nanotubes, and non-traditional computational approaches such as neuromorphic computing, cognitive computing, machine learning techniques, and the science behind quantum computing.

IBM already holds over 500 patents for technologies that will drive advancements at 7nm and beyond silicon -- more than twice the nearest competitor. These continued investments will accelerate the invention and introduction into product development for IBM's highly differentiated computing systems for cloud, and big data analytics.

Quantum Computing

The most basic piece of information that a typical computer understands is a bit. Much like a light that can be switched on or off, a bit can have only one of two values: "1" or "0.” Described as superposition, this special property of qubits enables quantum computers to weed through millions of solutions all at once, while desktop PCs would have to consider them one at a time.

IBM is a world leader in superconducting qubit-based quantum computing science and is a pioneer in the field of experimental and theoretical quantum information, fields that are still in the category of fundamental science - but one that, in the long term, may allow the solution of problems that are today either impossible or impractical to solve using conventional machines. The team recently demonstrated the first experimental realization of parity check with three superconducting qubits, an essential building block for one type of quantum computer.

Neurosynaptic Computing

Bringing together nanoscience, neuroscience, and supercomputing, IBM and university partners have developed an end-to-end ecosystem including a novel non-von Neumann architecture, a new programming language, as well as applications. This novel technology allows for computing systems that emulate the brain's computing efficiency, size and power usage. IBM’s long-term goal is to build a neurosynaptic system with ten billion neurons and a hundred trillion synapses, all while consuming only one kilowatt of power and occupying less than two liters of volume.

Silicon Photonics

IBM has been a pioneer in the area of CMOS integrated silicon photonics for over 12 years, a technology that integrates functions for optical communications on a silicon chip, and the IBM team has recently designed and fabricated the world's first monolithic silicon photonics based transceiver with wavelength division multiplexing.  Such transceivers will use light to transmit data between different components in a computing system at high data rates, low cost, and in an energetically efficient manner.
Silicon nanophotonics takes advantage of pulses of light for communication rather than traditional copper wiring and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

Businesses are entering a new era of computing that requires systems to process and analyze, in real-time, huge volumes of information known as Big Data. Silicon nanophotonics technology provides answers to Big Data challenges by seamlessly connecting various parts of large systems, whether few centimeters or few kilometers apart from each other, and move terabytes of data via pulses of light through optical fibers.
III-V technologies
IBM researchers have demonstrated the world’s highest transconductance on a self-aligned III-V channel metal-oxide semiconductor (MOS) field-effect transistors (FETs) device structure that is compatible with CMOS scaling. These materials and structural innovation are expected to pave path for technology scaling at 7nm and beyond.  With more than an order of magnitude higher electron mobility than silicon, integrating III-V materials into CMOS enables higher performance at lower power density, allowing for an extension to power/performance scaling to meet the demands of cloud computing and big data systems.

Carbon Nanotubes

IBM Researchers are working in the area of carbon nanotube (CNT) electronics and exploring whether CNTs can replace silicon beyond the 7 nm node.  As part of its activities for developing carbon nanotube based CMOS VLSI circuits, IBM recently demonstrated -- for the first time in the world -- 2-way CMOS NAND gates using 50 nm gate length carbon nanotube transistors.

IBM also has demonstrated the capability for purifying carbon nanotubes to 99.99 percent, the highest (verified) purities demonstrated to date, and transistors at 10 nm channel length that show no degradation due to scaling--this is unmatched by any other material system to date.

Carbon nanotubes are single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device that will work in a fashion similar to the current silicon transistor, but will be better performing. They could be used to replace the transistors in chips that power data-crunching servers, high performing computers and ultra fast smart phones.

Carbon nanotube transistors can operate as excellent switches at molecular dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of the leading silicon technology. Comprehensive modeling of the electronic circuits suggests that about a five to ten times improvement in performance compared to silicon circuits is possible.

Graphene

Graphene is pure carbon in the form of a one atomic layer thick sheet.  It is an excellent conductor of heat and electricity, and it is also remarkably strong and flexible.  Electrons can move in graphene about ten times faster than in commonly used semiconductor materials such as silicon and silicon germanium. Its characteristics offer the possibility to build faster switching transistors than are possible with conventional semiconductors, particularly for applications in the handheld wireless communications business where it will be a more efficient switch than those currently used.
Recently in 2013, IBM demonstrated the world's first graphene based integrated circuit receiver front end for wireless communications. The circuit consisted of a 2-stage amplifier and a down converter operating at 4.3 GHz.

Next Generation Low Power Transistors

In addition to new materials like CNTs, new architectures and innovative device concepts are required to boost future system performance. Power dissipation is a fundamental challenge for nanoelectronic circuits.

A potential alternative to today’s power hungry silicon field effect transistors are so-called steep slope devices. They could operate at much lower voltage and thus dissipate significantly less power. IBM scientists are researching tunnel field effect transistors (TFETs). In this special type of transistors the quantum-mechanical effect of band-to-band tunneling is used to drive the current flow through the transistor. TFETs could achieve a 100-fold power reduction over complementary CMOS transistors, so integrating TFETs with CMOS technology could improve low-power integrated circuits.

Recently, IBM has developed a novel method to integrate III-V nanowires and heterostructures directly on standard silicon substrates and built the first ever InAs/Si tunnel diodes and TFETs using InAs as source and Si as channel with wrap-around gate as steep slope device for low power consumption applications.

"In the next ten years computing hardware systems will be fundamentally different as our scientists and engineers push the limits of semiconductor innovations to explore the post-silicon future," said Tom Rosamilia, senior vice president, IBM Systems and Technology Group. "IBM Research and Development teams are creating breakthrough innovations that will fuel the next era of computing systems."

SOURCE  IBM

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 Nanotechnology  

UC Santa Barbara researchers have demonstrated a seamless design of an atomically-thin circuit with transistors and interconnects etched onto a seemingly impossible single layer of graphene.

Researchers in electrical and computer engineering at UC Santa Barbara have introduced and modeled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned seamlessly on a sheet of graphene, a two dimensional plane of carbon atoms.

The demonstration offers possibilities for ultra energy-efficient, flexible, and transparent electronics.

Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing "contact resistance" between them, both of which lead to degrading performance and rising energy consumption.

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Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address issues of traditional silicon-based transistors and metal interconnects.

"In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns - narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances," explained Kaustav Banerjee, professor of electrical and computer engineering and director of the Nanoelectronics Research Lab at UCSB. Banerjee's research team also includes UCSB researchers Jiahao Kang, Deblina Sarkar and Yasin Khatami.

Their work was recently published in the journal Applied Physics Letters.

"Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimization," explained Jiahao Kang, a PhD student in Banerjee's group and a co-author of the study. Banerjee's group pioneered a methodology using the Non-Equilibrium Green's Function (NEGF) technique to evaluate the performance of such complex circuit schemes involving many heterojunctions. This methodology was used in designing an "all-graphene" logic circuit reported in this study.

"This work has demonstrated a solution for the serious contact resistance problem encounterd in conventional semiconductor technology by providing an innovative idea of using an all-graphene device-interconnect scheme. This will significantly simplify the IC fabrication process of graphene based nanoelectronic devices." commented Philip Kim, professor of physics at Columbia University, and a renowned scientist in the graphene world.

As reported in their study, the proposed all-graphene circuits have achieved 1.7X higher noise margins and 1-2 decades lower static power consumption over current CMOS technology. According to Banerjee, with the ongoing worldwide efforts in patterning and doping of graphene, such circuits can be realized in the near future.

"We hope that this work will encourage and inspire other researchers to explore graphene and beyond-graphene emerging two dimensional crystals for designing such ‘band-gap engineered' circuits in the near future," added Banerjee.


SOURCE  UC Santa Barbara

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 Brain-Machine Interfaces  

University of California Berkeley neuroscientists have proposed a new brain-machine interface system that allows for thousands of ultra-tiny “neural dust” chips to be inserted into the brain to monitor neural signals at high resolution and communicate data highly efficiently via ultrasound.

Emerging technologies like functional magnetic resonance imaging (FMRI), magnetoencephalopathy and positron emission tomography are allowing the measurement of neuron clusters in the living brain.

This work is revolutionizing our understanding of the way the brain is structured and behaves. It has also lead to a new engineering discipline of brain-machine interfaces (BMI), which allows people to communicate and control machines by thought alone.  For paralyzed people this development has allowed users to control robotic arms with thought alone.

Now, University of California Berkeley neuroscientists have proposed a concept system that uses thousands of ultra-tiny neural dust chips to be inserted into the brain to monitor neural signals at high resolution and communicate data highly efficiently via ultrasound.

The neural dust design promises to overcome a serious limitation of current invasive brain-machine interfaces: the present range of implantable neural interface devices are, over time, rejected by the body.  Current BMI systems are also limited to several hundred implantable recording sites, they generate tissue responses around the implanted electrodes that degrade recording performance over time.

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Neural dust potentially provide the large-scale recording of neurons required for the Brain Research through Advancing Innovative Neurotechnologies (BRAIN) initiative, the scientists suggest.

The concept, published recently in the papter, "Neural Dust: An Ultrasonic, Low Power Solution for Chronic Brain-Machine Interfaces," is to sprinkle electronic sensors the size of dust particles into the cortex and to interrogate them remotely using ultrasound. The ultrasound also powers this so-called neural dust.

Each particle of neural dust consists of standard CMOS circuits and sensors that measure the electrical activity in neurons nearby. This is coupled to a piezoelectric material that converts ultra-high-frequency sound waves into electrical signals.

The neural dust is interrogated by another microprocessor placed beneath the skull but powered from outside the body. This generates the ultrasound that powers the neural dust and sensors that listen out for their response.

The researchers calculate that the neural dust chips can be as much as 10 million times more efficient that chips using electromagnetics (magnetic or electric signals), which have high attenuation in brain tissue. They would be encapsulated in an inert polymer or insulator film.

The study authors, Dongjin Seo, Jose M. Carmena, Jan M. Rabaey, Elad Alon, Michel M. Maharbiz, who a few years ago came to prominence with their work on remote controlling insects, have published the concept in order to get others thinking about the challenges and technical issues involved in the neural dust concept.

SOURCE  MIT Technology Review

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